The present invention relates to a physical adjustment method apparatus of an electronic computer or the like and, more particularly, to an electronic computer adjusting method apparatus which is suited for shortening the period of a logical failure analysis and improving the efficiency of a physical adjustment by using a computer having a simulation program.
In the prior art, an electronic computer is adjusted by scanning out the data of a variety of registers in the computer by a service processor and storing them in a scan-out memory, transferring the data in an external storage unit such as a floppy disc through the service processor, and analyzing a logical failure in the electronic computer view of the content of the data.
The above described technique is disclosed in Japanese patent application No. 200354/1984. According to the technique of Japanese patent application No. 200345/1984, the scan-out information in each cycle is stored during the testing of a computer in the scan-out memory of a service processor and then stored on a floppy disc. If necessary, the scan-out information is read out at a desired time from the floppy disc and scanned in the computer. Thus, the computer is set in a desired state.
Despite this fact, however, the scan-out memory has a limited capacity making it difficult to store data of various registers over a number of cycles. Moreover, since the computer is driven on a single clock, it is so exclusively used as to cause a deterioration in efficiency.
The current computer adjusting technology requires an improved method of adjusting a computer that overcomes these problems to thereby provide an advanced adjusting technology that is able to obtain a lot of data of the internal registers during multiple cycles and to eliminate unnecessary analysis time of the computer being adjusted.